Intel researchers see a path to trillion transistor chips by 2030

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Intel announced that its researchers envision a way to make chips 10 times denser through packaging improvements and a layer of a material just three atoms thick. And that could pave the way to putting a trillion transistors on a chip package by 2030.

Moore’s law should be dead. Chips aren’t supposed to get much better, at least not through traditional manufacturing advancements. That’s a dismal thought on the 75th anniversary of the invention of the transistor. In 1965, Intel chairman emeritus Gordon Moore predicted that the number of components, or transistors, on a chip would double every few years.

That law lasted for decades. Chips became faster and more efficient. Chipmakers reduced the size of chips, and goodness resulted. The electrons in a miniaturized chip had to travel shorter distances. So the chip got faster. And because of the shorter distances, the chip used less material, making it cheaper. And so the steady advance of Moore’s law meant that chips could become faster, cheaper and even more energy efficient.

But Moore’s law really depended on brilliant human engineers coming up with better chip designs and continued miniaturization of production. In recent years, it has become more difficult to make that progress. The design of the chip ran against the laws of physics. With atomic layers a few atoms thick, shrinkage was no longer possible. And so Jensen Huang, CEO of Nvidia, recently said, “Moore’s law is dead.”


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Intel showed how it could build chips with complex interconnected packages.

That’s not good timing since we’re about to start building the metaverse. Moore’s law is vital to addressing the world’s insatiable computing needs as rising data consumption and the push for more artificial intelligence (AI) drive the biggest acceleration in demand ever.

A week after Nvidia’s CEO said so, Intel CEO Pat Gelsinger said Moore’s law is alive and well. That’s no surprise, given that he has bet tens of billions of dollars on new chip factories in the US. Still, his researchers support him in the International Meeting on Electronic Devices. Intel made it clear that these advances will take five to ten years to materialise.

In papers at the research event, Intel described breakthroughs to keep Moore’s law on track for a trillion transistors on a package over the next decade. At IEDM, Intel researchers are demonstrating advances in 3D packaging technology with a new 10-fold improvement in density, Paul Fischer, director and senior chief engineer in component research at Intel, said in a news conference.

“Our mission is to keep our process technology options rich and full,” he said.

These packs are being used in innovative ways lately; Intel rival Advanced Micro Devices has announced that its latest graphics chip has a processor chip and six memory chips – all connected together in one package. Intel said it is working with government agencies, universities, industry researchers and chip equipment manufacturers. Intel shares the results of the research at places such as the IEDM event.

Intel also unveiled new materials for 2D transistor scaling beyond RibbonFET, including super-thin materials just three atoms thick. It also described new energy efficiency and memory capabilities for higher performing computers; and advancements for quantum computing.

“Seventy-five years after the invention of the transistor, innovation driving Moore’s law continues to meet the exponentially increasing demand for computers in the world,” Gary Patton, Intel vice president of component research and design support, said in a statement. “At IEDM 2022, Intel is demonstrating both the progressive and concrete research advancements needed to break current and future barriers, meet this insatiable demand, and keep Moore’s Law alive and well for years to come.”

The 75th anniversary of the transistor

The layers between chip circuits can be as little as three atoms thick.

In commemoration of the 75th anniversary of the transistor, Ann Kelleher, Intel’s Executive Vice President and General Manager of Technology Development, will lead a plenary session at IEDM. Kelleher will outline the paths for further industrial innovation – gathering the ecosystem around a systems-based strategy to meet the increasing demand for the world’s computing and innovate more effectively to advance at the pace of Moore’s law.

The session ‘Celebration of 75 years of transistor! A Look at the Evolution of Moore’s Law Innovation,” takes place at 9:45 a.m. PST on December 5.

To move forward, Intel has a multifaceted approach of “growing significance and certainly growing influence within Intel” to look across multiple disciplines.
Intel needs to make progress in chip materials, chip-making equipment, design and packaging, Fischer said.

“3D packaging technology enables the seamless integration of chiplets,” or multiple chips in a package, he said. “We’re blurring the line between where silicon ends and packaging begins.”

Continuous innovation is the cornerstone of Moore’s Law. Many of the key innovation milestones for continued power, performance and cost improvements over the past two decades — including stressed silicon, Hi-K metal gate and FinFET — in PCs, graphics processors and data centers began with Intel’s Components Research Group.

Further research, including RibbonFET gate-all-around (GAA) transistors, PowerVia back side power delivery technology, and packaging breakthroughs such as EMIB and Foveros Direct, are on the roadmap today.

At IEDM 2022, Intel’s Components Research Group said it is developing new 3D hybrid bonding packaging technology to enable seamless integration of chiplets; super thin 2D materials to fit more
transistors on a single chip; and new power efficiency and memory capabilities for higher performing computers.

How Intel will do it

Intel foresees voracious demand for computing power.

Researchers have identified new materials and processes that are blurring the line between packaging and silicon. Intel said it plans to move from tens of billions of transistors on a chip today to a trillion transistors on a package, which can hold many chips.

One way forward is through packaging that can achieve an additional 10 times interconnect density, leading to quasi-monolithic chips. Intel’s material innovations have also identified practical design choices that can meet the requirements of transistor scaling using a new material just three atoms thick, enabling the company to scale beyond RibbonFET.

Intel’s latest hybrid bonding research, presented at IEDM 2022, shows an additional 10 times better density for strength and performance over Intel’s IEDM 2021 research presentation.

Continued scaling of hybrid interconnects to a pitch of three nanometers allows for similar interconnect densities and bandwidths found in monolithic system-on-chip interconnects. A nanometer is one billionth of a meter.

Intel said it is looking for super-thin “2D” materials to fit more transistors on a single chip. Intel demonstrated a gate-all-round stacked nanosheet structure using a thin 2D channel just three atoms thick, while achieving near-ideal switching of transistors on a double-gate structure at room temperature with low leakage current.

These are two major breakthroughs needed to stack GAA transistors and go beyond the fundamental limits of silicon.

Researchers also revealed the first comprehensive analysis of electrical contact topologies for 2D materials that could further pave the way for high-performing and scalable transistor channels.

To use the chip area more effectively, Intel is redefining scaling by developing memory that can be placed vertically above transistors. In an industry first, Intel is demonstrating stacked ferroelectric capacitors that match the performance of conventional ferroelectric trench capacitors and can be used to build FeRAM on a logic chip.

A device-level model, the industry’s first, captures mixed phases and defects for enhanced ferroelectric hafnia devices, representing significant progress for Intel in supporting industry tools to develop new memories and ferroelectric transistors.

Intel sees a path to trillion transistor chips with different approaches.

By bringing the world one step closer to transitioning from 5G and solving the challenges of energy efficiency, Intel is building a viable path to 300 millimeter GaN-on-silicon wafers. Intel’s breakthroughs in this area demonstrate gains 20 times greater than industry-standard GaN and set an industry record for high-performance power delivery.

Intel is making breakthroughs in super energy efficient technologies, especially transistors that don’t forget and retain data even when power is off. Intel researchers have already broken two of the three barriers preventing the technology from being fully viable and operational at room temperature.

Intel continues to introduce new concepts to physics with breakthroughs in providing better qubits for quantum computing. Intel researchers are working on better ways to store quantum information by gaining a better understanding of various interface defects that can act as environmental perturbations affecting quantum data.

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